1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to a method and apparatus for making interconnections in a same metal level.
2. Description of the Related Art
An ever-present need in the semiconductor industry is to provide more densely populated chips while maintaining or increasing yield. Semiconductor devices having memory cells, for example, static random access (SRAM) cells, are always subject to efforts for reducing the cell size as much as possible without decreasing the yield. One element, which consumes real estate in a memory cell, is the cross-coupling between inverters. Cross-coupling of an inverter includes connecting a source or drain region of a transistor to a gate of the transistor. In a physical layout of the transistor, e.g., on a semiconductor chip, this means that a source/drain diffusion region is connected to a gate conductor.
Since, the gate has to be electrically connected to the diffusion, an electrical link is provided which includes a first contact to the diffusion, a metal line in an upper metal layer connected to the first contact and to a second contact, and the second contact connects to the gate conductor. This connection scheme requires, contacts to reach upper metal layers (e.g., M1). Further, the contacts and diffusion regions are lithographically formed and include dimensions limited by lithography and processing which tend to increase their size and result in area costs.
Therefore, a need exists for a direct strap and a method for forming the same which provide an interconnection on a same level. A further need exists for the buried strap to enable a reduction in cell size and permit the area above the cell to be available for routing of upper metal lines.
A method and apparatus for forming a direct buried strap for a semiconductor device, in accordance with the present invention, includes forming a gate stack on a semiconductor substrate, and forming a protective layer on sidewalls of the gate stack. The protective layer extends horizontally over a portion of the semiconductor substrate adjacent to the gate stack. A conductive layer is formed over the protective layer and in contact with a gate conductor of the gate stack and in contact with a diffusion region formed in the semiconductor substrate adjacent to the gate conductor. A dielectric layer is formed over the conductive layer, and the dielectric layer is patterned to expose a portion of the conductive layer. The portion of the conductive layer which is exposed includes a portion of the conductive layer over the gate conductor and a portion of the substrate adjacent to the gate conductor. The exposed areas of the conductive layer are silicided to form a direct buried strap and a silicided diffusion region in the substrate. The direct buried strap electrically connects the gate conductor to the diffusion region in a same level of the semiconductor device.
Another method for forming a direct buried strap for a semiconductor device, in accordance with the invention, includes the steps of providing a silicon substrate, forming a gate stack on the substrate, the gate stack including a protective dielectric layer on vertical surfaces, the protective dielectric layer including a horizontal portion extending outward from the gate stack in contact with the substrate, forming a conductive layer capable of being silicided in contact with a gate conductor of the gate stack and the substrate adjacent to the gate stack beyond the horizontal portion of the protective dielectric layer, forming a sacrificial dielectric layer over the conductive layer, patterning the sacrificial dielectric layer to expose a portion of the conductive layer, the portion of the conductive layer which is exposed includes a portion of the conductive layer over the gate stack in contact with the gate conductor and a portion of the substrate adjacent to the gate stack beyond the horizontal portion of the protective dielectric layer, and siliciding the exposed areas of the conductive layer to form a direct buried strap along the gate stack over the protective dielectric layer and a silicided diffusion region on the substrate adjacent to the gate stack beyond the horizontal portion of the protective dielectric layer, the direct buried strap electrically connecting the gate conductor to the silicided diffusion region in a same level of the semiconductor device.
In other methods, the step of siliciding may include the step of depositing silicon on the conductive layer. The step of depositing silicon on the conductive layer may include cold deposition of silicon in a temperature range of between about 20xc2x0 C. and about 400xc2x0 C., with a step of performing a rapid thermal anneal (RTA) or a hot deposition of silicon in a temperature range of between about 400xc2x0 C. and about 700xc2x0 C. The step of patterning the dielectric layer to expose a portion of the conductive layer may include the step of protecting a second portion of the conductive layer from siliciding by employing the dielectric layer as a mask. The method may include stripping the dielectric layer after siliciding, and stripping the second portion of the conductive layer. The step of annealing the semiconductor device by employing a rapid thermal anneal may also be included. The substrate may include silicon and the second portion of the conduction layer may include a third portion which contacts a portion of the substrate and the step of annealing the third portion of the conductive layer and the portion of the substrate in contact with the third portion to form a silicided junction may be included. The method may include the steps of forming a second dielectric layer over the direct buried strap and the silicided diffusion region, and forming metal layers over the second dielectric layer wherein the gate conductor is connected to the silicided diffusion region while avoiding interconnection to other metal layers. The conductive layer may include one of Tungsten, Cobalt and Titanium.
In still other methods, the step of patterning the sacrificial dielectric layer to expose a portion of the conductive layer may include the step of protecting a second portion of the conductive layer from siliciding by employing the dielectric layer as a mask and may further include the steps of stripping the sacrificial dielectric layer after siliciding and stripping the second portion of the conductive layer. The second portion of the conduction layer may include a third portion which contacts a portion of the substrate and further includes the step of annealing the third portion of the conductive layer and the portion of the substrate in contact with the third portion to form a silicided junction. The method may further include the steps of forming an interlevel dielectric layer over the gate stack and the silicided diffusion region and forming metal layers over the interlevel dielectric layer wherein the gate conductor is connected to the silicided diffusion region while avoiding interconnection to other metal layers.
A semiconductor device, in accordance with the present invention, having a transistor cross-coupled in a same level includes a substrate having a gate stack formed thereon, the gate stack including a gate conductor. A protective dielectric layer is formed on vertical surfaces on the gate stack. The protective dielectric layer includes a horizontal portion extending outward from the gate stack in contact with the substrate. A first diffusion region is formed on a first side of the gate stack beyond the horizontal portion of the protective dielectric layer. A direct strap is formed over the protective dielectric layer. The direct strap connects the first diffusion region to the gate conductor in a same level of the semiconductor device.
In other embodiments, the direct strap preferably includes one of Tungsten silicide, Cobalt silicide and Titanium silicide. The device may include a second diffusion region formed on a second side of the gate stack. The second side is opposite the first side, and the first and second diffusion regions and the gate stack form a transistor. The device may include an interlevel dielectric layer formed over the transistor.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.